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| 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) Features IDT71V016 Description The IDT71V016 is a 1,048,576-bit high-speed Static RAM organized as 64K x 16. It is fabricated using IDT's high-perfomance, high-reliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for high-speed memory needs. The IDT71V016 has an output enable pin which operates as fast as 7ns, with address access times as fast as 12ns. All bidirectional inputs and outputs of the IDT71V016 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. The IDT71V016 is packaged in a JEDEC standard 44-pin Plastic SOJ and 44-pin TSOP Type II. 64K x 16 advanced high-speed CMOS Static RAM Commercial (0 to +70C) and Industrial (-40C to +85C) Equal access and cycle times -- Commercial and Industrial: 15/20ns One Chip Select plus one Output Enable pin Bidirectional data inputs and outputs directly LVTTL-compatible Low power consumption via chip deselect Upper and Lower Byte Enable Pins Single 3.3V (0.3V) power supply Available in 44-pin Plastic SOJ and 44-pin TSOP package. Functional Block Diagram OE Output Enable Buffer A0 - A15 Address Buffers CS Chip Enable Buffer WE O Write Enable Buffer Byte Enable Buffers N NC I E 6SA S TC R S 01 IGN AEVS P L 71 DE O ER W SD E BR N Row / Column Decoders I/O15 8 High Byte I/O Buffer 8 I/O8 E OR O F 64K x 16 Memory Array 16 Sense Amps and Write Drivers I/O7 8 Low Byte I/O Buffer 8 I/O0 BHE BLE 3211 drw 01 AUGUST 2000 1 (c)2000 Integrated Device Technology, Inc. DSC-3211/08 IDT71V016, 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges Pin Configuration A4 A3 A2 A1 A0 CS I/O0 I/O1 I/O2 I/O3 VDD Vss I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 Vss VDD Pin Description SO44-1 SO44-2 SOJ/TSOP Top View Truth Table(1) CS H L L L L L L L L OE X L L L X X X H X O WE X H H H L L L H X IN N A T CE 6S NS R S 01 IG AEVS P L 71 DE O ER W SD E BR N I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC 3211 drw 02 C E BLE X L H L L L H X H OR O F BHE X H L L L H L X H I/O0-I/O7 High-Z I/O8-I/O15 High-Z High-Z DATAOUT DATAOUT DATAIN High-Z DATAIN High-Z High-Z Function Deselected - Standby Low Byte Read High Byte Read Word Read Word Write Low Byte Write High Byte Write Outputs Disabled Outputs Disabled 3211 tbl 02 DATAOUT High-Z DATAOUT DATAIN DATAIN High-Z High-Z High-Z NOTE: 1. H = VIH, L = VIL, X = Don't care. 6.42 2 IDT71V016, 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges (1) Absolute Maximum Ratings Symbol VTERM(2) VTERM(3) TA TBIAS TSTG PT IOUT Rating Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Value -0.5 to +4.6 Unit V V o Recommended Operating Temperature and Supply Voltage Grade Commercial Temperature 0C to +70C -40C to +85C GND 0V 0V VDD 3.3V 0.3V 3.3V 0.3V 3211 tbl 04 -0.5 to VCC+0.5 0 to +70 -55 to +125 -55 to +125 1.0 50 Industrial C C C o o Recommended DC Operating Conditions Symbol VDD Parameter Supply Voltage Supply Voltage Input High Voltage - Inputs Input High Voltage - I/O Input Low Voltage Min. Typ. 3.3 0 -- ____ ____ Max. 3.6 0 4.6 VDD+0.3 0.8 Unit V V V V V 3211 tbl 05 W mA 3211 tbl 03 GND VIH VIH VIL NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VDD terminals only. 3. Input, Output,and I/O terminals; 4.6V maximum. DC Electrical Characteristics (VDD = 3.3V 0.3V, Commercial and Industrial Temperature Ranges) Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage DC Electrical Characteristics(1) (VDD = 3.3V 0.3V, VLC = 0.2V, VHC = VDD-0.2V) Symbol ICC Parameter O IN N A T CE 6S NS R S 01 IG AEVS P L 71 DE O ER W SD E BR N 2.0 -0.5 (1) NOTE: 1. VIL (min.) = -1.5V for pulse width less than tRC/2, once per cycle. C E 3.0 0 2.0 Capacitance Symbol CIN (TA = +25C, f = 1.0MHz, SOJ package) Parameter(1) Input Capacitance I/O Capacitance Conditions VIN = 3dV Max. 6 7 Unit pF pF CI/O VOUT = 3dV 3211 tbl 06 NOTE: 1. This parameter is guaranteed by device characterization, but not production tested. IDT71V016 Test Condition Min. ___ ___ ___ Max. 5 5 Unit A A V V 3211 tbl 07 VDD = Max., VIN = GND to VDD VDD = Max., CS = VIH, VOUT = GND to VDD OR O F IOL = 8mA, VDD = Min. 0.4 ___ IOH = -4mA, VDD = Min. 2.4 71V016S15 Com'l 130 Ind. 130 71V016S20 Com'l. 120 Ind. 120 Unit mA Dynam ic Operating Current CS VIL, Outputs Open, VDD = Max., f = fMAX(2) Standby Power Supply Current (TTL Level) CS VIH, Outputs Open, VDD = Max., f = fMAX(2) Standby Power Supply Current (CMOS Level) CS VHC, Outputs Open, VDD = Max., f = 0(2) VIN VLC or VIN VHC ISB 35 35 30 30 mA ISB1 5 7 5 7 mA NOTES: 1. All values are maximum guaranteed values. 2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing . 3211 tbl 08 6.42 3 IDT71V016, 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load GND to 3.0V 1.5ns 1.5V 1.5V See Figure 1, 2 and 3 3211 tbl 09 AC Test Loads 3.3V DATA OUT 30pF* Figure 1. AC Test Load tAA, tACS (Typical, ns) 5 4 3 2 1 * O IN N A T CE 6S NS R S 01 IG AEVS P L 71 DE O ER W SD E BR N 3.3V 320 C E 320 DATA OUT 350 5pF* 350 3211 drw 04 3211 drw 05 *Including jig and scope capacitance. Figure 2. AC Test Load (for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ) 7 6 OR O F * * * * * * 8 20 40 60 80 100 120 140 160 180 200 CAPACITANCE (pF) Figure 3. Output Capacitive Derating 3211 drw 06 6.42 4 IDT71V016, 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges AC Electrical Characteristics Symbol READ CYCLE tRC tAA tACS tCLZ(1) tCHZ(1) tOE tOLZ (1) (VDD = 3.3V 0.3V, Commercial and Industrial Temperature Ranges) 71V016S15 71V016S20 Min. Max. Unit Parameter Min. Max. Read Cycle Time Address Access Time Chip Select Access Time Chip Select Low to Output in Low-Z Chip Select High to Output in High-Z Output Enable Low to Output Valid Output Enable Low to Output in Low-Z 15 ____ ____ ____ 20 ____ ____ ____ ns ns ns ns ns ns ns ns ns ns ns ns 15 15 ____ 20 20 ____ 5 ____ 5 ____ 6 8 ____ ____ ____ tOHZ (1) tOH tBE tBLZ (1) Output Enable High to Output in High-Z Output Hold from Address Change Byte Enable Low to Output Valid Byte Enable Low to Output in Low-Z tBHZ(1) Byte Enable High to Output in High-Z WRITE CYCLE tWC tAW tCW tBW tAS tWR tWP tDW tDH tOW(1) tWHZ(1) Write Cycle Time Address Valid to End of Write Chip Select Low to End of Write Byte Enable Low to End of Write Address Set-up Time Address Hold from End of Write Write Pulse Width Data Valid to End of Write Data Hold Time Write Enable High to Output in Low-Z Write Enable Low to Output in High-Z NOTE: 1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested. O IN N A T CE 6S NS R S 01 IG AEVS P L 71 DE O ER W SD E BR N ____ 0 6 4 -- 8 -- 0 C 0 5 0 ____ E 8 10 ____ 8 -- ____ 10 ____ ____ ____ 6 ____ 8 15 10 ____ ____ ____ ____ ____ ____ ____ ____ ____ 20 ____ ____ ____ ____ ____ ____ ____ ____ ____ ns ns ns ns ns ns ns ns ns ns ns 3211 tbl 10 12 12 12 0 0 10 10 0 0 10 8 12 10 0 0 Timing Waveform of Read Cycle No. 1(1,2,3) tRC ADDRESS tAA tOH DATAOUT PREVIOUS DATAOUT VALID tOH DATAOUT VALID 3211 drw 07 OR O F 1 ____ 1 ____ ____ 6 ____ 8 NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS is LOW. 3. OE, BHE, and BLE are LOW. 6.42 5 IDT71V016, 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges Timing Waveform of Read Cycle No. 2(1) tRC ADDRESS tAA OE tOE CS tCLZ (3) tOH tOHZ (3) tOLZ tACS (2) (3) BHE, BLE DATAOUT NOTES: 1. WE is HIGH for Read Cycle. 2. Address must be valid prior to or coincident with the later of CS, BHE, or BLE transition LOW; otherwise tAA is the limiting parameter. 3. Transition is measured 200mV from steady state. Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4) tWC ADDRESS CS BHE , BLE WE O IN N A T CE 6S NS R S 01 IG AEVS P L 71 DE O ER W SD E BR N tBE (2) tBLZ (3) C tCHZ E (3) (3) tBHZ DATA OUT VALID 3211 drw 08 tAW tCW (2) tAS OR O F tWHZ (5) (3) tCHZ (5) tBW tWR tWP tBHZ (5) tOW tDW tDH (5) DATAOUT PREVIOUS DATA VALID DATA VALID DATAIN DATAIN VALID 3211 drw 09 NOTES: 1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE. 2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP. 3. During this period, I/O pins are in the output state, and input signals must not be applied. 4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 5. Transition is measured 200mV from steady state. 6.42 6 IDT71V016, 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,4) tWC ADDRESS tAW CS tAS tBW tCW (2) BHE , BLE tWP WE tWR DATAOUT DATAIN Timing Waveform of Write Cycle No. 3 (BHE, BLE Controlled Timing)(1,4) tWC ADDRESS CS BHE , BLE WE O IN N A T CE 6S NS R S 01 IG AEVS P L 71 DE O ER W SD E BR N tDW tDH DATAIN VALID tAW tAS tCW (2) C E 3211 drw 10 tBW tWP tWR DATAOUT DATAIN OR O F tDW tDH DATAIN VALID 3211 drw 11 NOTES: 1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE. 2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP. 3. During this period, I/O pins are in the output state, and input signals must not be applied. 4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 5. Transition is measured 200mV from steady state. 6.42 7 IDT71V016, 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges Ordering Information IDT 71V016 Device Type S Power XX Speed XXX Package X Process/ Temperature Range Blank I Commercial (0C to +70C) Industrial (-40C to +85C) O IN N A T CE 6S NS R S 01 IG AEVS P L 71 DE O ER W SD E BR N Y PH 15 20 C 400-mil SOJ (SO44-1) 400-mil TSOP Type II (SO44-2) E Speed in nanoseconds 3211 drw 12 OR O F 6.42 8 IDT71V016, 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges Datasheet Document History 11/1/99 Pg. 3 Pg. 5 Pg. 6 Pg. 7 Pg. 9 08/30/00 Updated to new format Expressed commercial and industrial ranges on DC Electrical table Expressed commercial and industrial ranges on AC Electrical table Revised footnotes on Write Cycle No. 1 diagram Revised footnotes on Write Cycle No. 2 and No. 3 diagrams Added Datasheet Document History Part in obsolescence, order part 71V016SA. See PDN# S-0003 O N NC I A T CE 6S NS R S 01 IG AEVS P L 71 DE O ER W SD E BR N OR O F E CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 9 for Tech Support: sramhelp@idt.com 800-544-7726, x4033 The IDT logo is a registered trademark of Integrated Device Technology, Inc. |
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